代码 PRIO-020: I/O Link comm error %x, %x, %x, %x (hex)

Cause: Indicates that an error has been detected in communication between the MAIN CPU PCB and the process I/O board, Model-A I/O racks, or Model-B I/O interface units. The most common causes of this are the following: o Power to a remote I/O rack or Model-B I/O interface unit is interrupted. o The cable between the MAIN CPU PCB and the process I/O board, racks, or Model-B interface units has been disconnected or is faulty. o Electrical interference between the I/O cables and other cables. This can be eliminated by physically separating the I/O cables from other wiring. In very electrically noisy environments, it might be necessary to use optical isolators with these cables. Remedy: Check the cabling between the MAIN CPU PCB (JB-18 connector) and the process I/O board and/or model A or B interface modules. Check power to the remote Model A I/O racks and model B I/O interface modules. If corrections to these do not correct the problem, check the four numbers displayed in this error message. The first value must be interpreted bit-wise. If a bit is 1, the corresponding condition has been detected: Bit 0: (CFER) A CRC or framing error has been detected by the SLC-2 chip on the MAIN CPU PBC. This is most frequently the result of the problems listed above. Otherwise, it might indicate faulty SLC-2 chip, wiring between this and the JB-1B connector on the main PCB, or faulty process I/O, model-A I/O rack, or model-B interface unit. Bit 1: (CALM) An error has been detected by a slave SLC-2 (process I/O board, Model-A rack, or Model B interface unit). More information is provided by the second number displayed with the PRIO-020 error. Bit 2: (CMER) A communication error has been detected by a slave SLC-2. The potential causes are similar to those for a CFER. Bit 3: (IPRER): Internal parity error accessing